1. Field of the Invention
The present invention generally relates to computer systems in which configuration cycles can be performed on a peripheral bus. More specifically, the present invention relates to a Peripheral Component Interconnect (“PCI”) bus on which two PCI-compatible devices share the same configuration select signal thereby causing a conflict when the common select signal is asserted to run a configuration cycle. The invention avoids the conflict by using an alternate signal as the select signal for one of the PCI devices.
2. Background of the Invention
Most, if not all, computer systems include one or more microprocessors (e.g., Intel Pentium III, AMD K6), system memory (often referred to as “RAM” for Random Access Memory), disk drives, a keyboard, and various other components. The system memory and microprocessor (also called the Central Processing Unit or “CPU”) typically couple together via a “host bridge” logic device. The host bridge also includes an interface to a system bus such as the well-known Peripheral Component Interconnect (“PCI”) bus. The host bridge generally permits the CPU, system memory and various devices connected to the PCI bus to communicate with one another in a coordinated manner.
For example, the CPU, PCI-compatible devices, and other devices in the computer system may desire to write data to or read data from system memory. Because system memory generally can only respond to one read or write request at a time, the host bridge usually includes a memory controller and arbiter to determine which memory request is allowed to execute—the other pending requests may be stored in a temporary buffer waiting their turn to be executed by the memory controller.
The PCI bus coupled to the host bridge generally is a 32-bit or 64-bit bus with multiplexed address and data lines, called “AD” lines in the PCI Local Bus Specification, Revision 2.2, dated Dec. 18, 1998, incorporated herein by reference in its entirety. This means that addresses and data are placed on the same set of signal lines, but at different times. In accordance with the PCI Local Bus Specification, the address is placed on the AD lines first and any data associated with a write cycle, for example, is placed on the AD lines afterwards.
Besides read and write cycles, configuration cycles can be performed on the PCI bus. Configuration cycles are often performed during the Power-On Self-Test (“POST”) process. During POST, one action performed by the CPU is to attempt to determine how many PCI devices are present in the computer system and, for those PCI devices that are present and available, to read the configuration information stored in the devices. In accordance with the PCI Local Bus Specification, all PCI-compatible devices (referred to throughout this disclosure simply as “PCI devices”) are required to have 256 bytes of configuration registers. In a configuration read cycle, the CPU, although in general it could be a device other than the CPU, can read a PCI device's configuration registers. In a configuration write cycle, the CPU can reconfigure a PCI device by writing new values to that device's configuration registers.
A PCI device must include an Initialization Device Select (“IDSEL”) input signal. The IDSEL input is used as a chip select during configuration read and write transactions. Thus, when the CPU reads configuration information from a PCI device or writes configuration to a PCI device, the IDSEL input of the target PCI device must be asserted. Each PCI device provides an IDSEL input signal that is independently asserted by, for example, a host bridge device. Accordingly, the host bridge provides separate signals to the IDSEL input pins of the various PCI devices.
The PCI Local Bus Specification does not dictate how a PCI device's IDSEL pin is to be driven; that decision is left to the discretion of the host bridge designer. One approach has been to connect a unique address AD line to each PCI device's IDSEL pin. For example, the upper 21 AD lines of the AD portion of the PCI bus (i.e., AD[31::11]), are available for connection to IDSEL pins. One PCI device may have its IDSEL pin connected to AD14, while a separate PCI device may have its IDSEL pin connected to AD15. When the CPU, via the host bridge, wishes to perform a PCI configuration read or write cycle to a particular PCI device, the host bridge asserts the AD line connected to the target PCI device to signal to that PCI device that a configuration cycle is to be run.
During POST as the CPU determines the existence of the PCI devices connected to the PCI bus, each AD line potentially used as an input to a device's IDSEL pin is independently “strobed.” That is, the CPU directs the host bridge to assert each AD[31::11] line one at a time. If a particular AD line is not connected to a PCI device's IDSEL pin, the CPU will not receive a response and determines that there is no device present on the PCI bus connected to that particular AD line. If the CPU receives a response after a particular AD line is asserted, then the CPU determines that there is a PCI device whose IDSEL input pin is tied to that particular AD line. The CPU can request that PCI device to provide the contents of its configuration registers to the CPU. The CPU also can write new configuration information to that PCI device to configure or reconfigure the device.
The devices connected to the PCI bus are each assigned an identifying number such as “Device 0,” “Device 1,” “Device 2,” and so on. A suitable host bridge is the 82443BX Host Bridge/Controller provided by Intel®. The 82443BX includes a number of registers including a Configuration Address Register (“CONFADD”). The CONFADD register can be read or written by the CPU in the computer system. The CONFADD register includes a Device Number field associated with bits 15:11. The CPU can run a configuration cycle to any desire device number by writing the device number value to this field. The 82443BX host bridge interprets this field and asserts one bit among AD[31::11] to initiate the configuration cycle on the PCI bus. In accordance with the 82443BX host bridge specification, if the host bridge decodes a device number as 2, the host bridge responds by asserting AD13. Similarly, a device number of 3 will cause the host bridge to assert AD14, and so on.
Device numbers 0 and 1 are contained within the 82443BX host bridge chip itself and thus are pre-assigned to the 82443BX host bridge. Thus, other devices on the PCI must not be assigned Device 0 or Device 1. Device 0 is assigned to the CPU Host-to-PCI Bridge interface within the 82443BX and Device 1 is assigned to the Host-to-AGP Interface (“AGP” stands for Advanced Graphics Port and is a special function PCI bus designed for graphics-related bus transfers). Device 0 and Device 1 sometimes are referred to as “virtual” devices because they are not physically separate devices; they are part of the host bridge device itself. The 82443BX host bridge internally references the AD11 and AD12 pins as corresponding IDSELs for the Devices 0 and 1, respectively during PCI configuration cycles. For this reason, the 82443BX host bridge specification states that the AD11 and AD12 lines must not be connected to any other PCI bus device as IDSEL inputs. Otherwise, a conflict would occur if a configuration cycle was attempted to a PCI device whose IDSEL pin was tied to AD11 or AD12.
A typical computer system includes components designed and manufactured by a variety of manufacturers. For example, Texas Instruments provides a cardbus controller (PCI 1131) module that is designed to be used in an expansion base for interconnection to laptop computers. The PCI 1131 cardbus controller is a PCI bus-compliant device that is “pre-wired” to have AD11 connected to its IDSEL input pin. As explained above, this will cause a conflict in a computer system which also uses the Intel® 82443BX host bridge. The same sort of PCI bus configuration cycle conflict also may occur with other models of host bridge chips and PCI devices.
One solution to the problem might be for Intel or Texas Instruments to change the design of its part to avoid this conflict. This approach, however, might result in creating a similar conflict with respect to other PCI devices that might be included in the computer system. Thus, another solution is needed that can avoid the PCI configuration cycle conflict described above. Despite the advantages such a solution would provide, no system is known to date that solves the conflict problem.